Microprocessors are operated in response to a system clock. The increase in microprocessor speeds and the simultaneous reduction in power supply voltages impose restrictions on the design of microprocessor system clocks. In addition to microprocessor speed and power supply constraints, there is a demand for increased system clock frequency shifting flexibility. The frequency of the system clock of a microprocessor may be shifted for testing purposes or to preserve power.
Phase-locked loop circuits are widely used in electronic systems. These circuits are used to generate an accurate replica of an incoming signal. For example, in a computer, a phase-locked loop is used by a microprocessor to generate an on-chip clock signal from an off-chip clock signal.
To conserve power, it is desirable to reduce a microprocessors clock frequency when it is not being used. In conventional computer systems phase-locked loop circuits lose phase lock when the microprocessor clock frequency is changed. This increases the amount of time required to switch between a power saving mode and normal operation. In addition, the loss of phase lock may cause a signal to violate timing requirements and thereby create a metastable state which can cause the microprocessor to malfunction.
In view of these and other problems of conventional microprocessor phase-locked loop systems, it would be highly desirable to provide a phase-locked loop system that maintains phase lock when clock frequencies are changed, enables rapid switching between normal operating modes and power saving modes, and provides deterministic operation so as to avoid metastable states.